1. Field of the Invention
The present invention relates generally to systems for supplying power to a load, and, in particular, to such systems that use plural power sources where the power supplied from the power sources is equalized.
2. Description of Background Art
It is known to couple two power sources together to supply power to a common load. FIG. 1 shows a block diagram of a prior art system 10 for supplying power to a load. The system shown in FIG. 1 includes first and second power sources 11 and 12 that are coupled to one another in parallel. The power sources 11 and 12 use first and second feedback networks 13 and 14 to regulate the voltages applied to the load 16 by the power sources 11 and 12. Each power source 11 and 12 also includes a respective current sensing means 17 and 18 to monitor the current supplied to the load 16 by that power source. Each current sensing means 17 and 18 generates a voltage that is representative of the current supplied by the associated power source 11 and 12 to the load 16. The voltages generated by the current sensing means 17 and 18 are compared by the amplifier 15, which provides an error voltage that is representative of the difference between the currents supplied to the load 16 by the power sources 11 and 12. This error voltage is applied to the feedback networks 13 and 14 to substantially equalize the currents supplied by each of the power sources 11 and 12 to the load 16. Accordingly, the power from the two power sources 11 and 12 is equalized.
FIG. 2 shows a particular embodiment of the prior art system shown in FIG. 1. The power sources 11 and 12 are coupled in parallel to one another for supplying power to the load 16. The output voltage of the power source 11 is compared to a first reference voltage V.sub.REF1 by the amplifier U1, and the resulting error voltage is applied to a control terminal of the first power source 11 to regulate its output voltage. Similarly, the output voltage of the power source 12 is compared to a second reference voltage V.sub.REF2 by the amplifier U2, and the resulting error voltage is applied to a control terminal of the second power source 12 to regulate its output voltage. A sense resistor R1 and its associated amplifier U3 provide a first current-sense voltage that is representative of the current supplied to the load 16 by the first power source 11, and a sense resistor R2 and its associated amplifier U4 provide a second current-sense voltage that is representative of the current supplied to the load 16 by the second power source 12. The first and second current sense voltages are compared by the amplifier U5, which provides an error voltage that is representative of the difference between the currents that are supplied to the load 16 by each of the power sources 11 and 12. The error voltage from the amplifier US is fed back to the feedback networks 13 and 14 to equalize the currents supplied to the load 6 by each of the power sources 11 and 12. The error voltage from the amplifier US is inverted by the inverter N1 prior to being fed back to the feedback network 14.
The prior art system 10 illustrated in FIGS. 1 and 2 works well to equalize the currents (and hence the power) supplied to the load 16 by each of the power sources 11 and 12. However, using the sense resistors R1 and R2 and their associated circuitry to sense the currents supplied to the load 16 is disadvantageous because it increases the parts count (i.e., the number of parts) as well as size of the system and decreases the efficiency of the system.
It is known to cancel the input ripple current drawn by a system in order to power a load. It is known in the art to effect input ripple current cancellation by coupling two power sources in parallel and by providing the two power sources with switching frequencies that are 180.degree. out of phase. The prior art system 20 illustrated in FIG. 3 provides for the cancellation of input ripple current in this manner. The system 20 includes a first boost-type power converter 21 (a first power source), which comprises a PWM controller 22, a FET power switch M1, an inductance L1, a rectifier D1, and a filter capacitor C1. The power converter 21 operates in a manner that is well-known, and will not be described further herein. The power supplied to the load 26 by the first power converter 21 is regulated by the feedback network 27 and the PWM controller 22, the output of which is coupled to the gate electrode of the FET power switch M1. A voltage divider formed by the resistors R3 and R4 of feedback network 27 divides the output voltage of the first power converter 21 and compares the divided output voltage against a reference voltage V.sub.REF3 in the amplifier U6. The output voltage from the amplifier U6 is then coupled to the control input of the PWM controller 22 to regulate the ON time of the power switch M1.
The system 20 further includes a second boost-type power converter 23 (a second power source), which comprises a PWM controller 24, a FET power switch M2, an inductance L2, a rectifier D2, and a filter capacitor C2. The power converter 23 operates in a manner that is well-known, and will not be described further herein. The power supplied to the load 26 by the second power converter 23 is also regulated by the feedback network 27 and by the PWM controller 24, the output of which is coupled to the gate electrode of the FET power switch M2. The output voltage from the amplifier U6 is also coupled to the control input of the PWM controller 24 to regulate the ON time of the power switch M2.
As is well-known, the currents flowing through the inductors L1 and L2 in, respectively, the power converters 21 and 23 have triangular waveforms. A fixed-frequency oscillator 25 is directly coupled to the clock input of the PWM controller 22 and is coupled to the clock input of the PWM controller 24 through the inverter N2 to provide the PWM controllers 22 and 24 with clock waveforms that are 180.degree. out of phase. As a result, the triangular current waveforms for the inductors L1 and L2 will be 180.degree. out of phase. Therefore, the triangular component of the input current is cancelled, leaving only the DC component of the input current. The circuit of FIG. 3 does not address the problem of current or power equalization to the load 26.
U.S. Pat. No. 4,779,184 to White, issued on Oct. 18, 1988 and entitled SWITCH MODE POWER SUPPLY WITH REDUCED NOISE ("the '184 Patent") discloses a phase-locked loop for controlling the phase and duty cycle of two switch-mode power supplies that supply power to a common load to produce an output voltage which is substantially free of harmonics. The phase-locked loop maintains a desired phase shift between the drive signals of the two power supplies. A drive signal for one of the power supplies is provided by an oscillator which oscillates at a fixed frequency. The drive signal for the other power supply is provided by a voltage-controlled oscillator which oscillates at the frequency of the fixed oscillator. The power supplies disclosed in the '184 Patent are fixed frequency power supplies. The '184 Patent is not directed to substantially equalizing the load currents or power supplied by the power supplies or cancelling a ripple component of the input current drawn by the system.
U.S. Pat. No. 5,079,686 to Vinciarelli, issued on Jan. 7, 1992 and entitled ENHANCEMENT-MODEZERO-CURRENTSWITCHING CONVERTER ("the '686 Patent"), discloses a system of enhancement-mode power converters that have their outputs coupled together to deliver power to a load. Each power converter has an associated setpoint voltage, and the power converters synchronize to the operating frequency of the power converter that has the highest setpoint voltage, and hence, the highest power output. Synchronizing information is delivered to the power converters by a synchronizing bus. The '686 Patent discloses a complex system of setpoint voltages delivered through a bus to achieve frequency synchronization and, hence, power equalization, of its power converters. There is no disclosure of phase detection. The '686 Patent does not address cancellation of an input ripple component of the input current drawn by the system. The power converters that can be used in the system disclosed in the '686 Patent are unfortunately limited to those power converters that have a linear relationship between their switching frequency and the power that they deliver to a load.